數(shù)字集成電路設(shè)計(jì)-13-常用模塊集錦
來(lái)源：程序員人生 發(fā)布時(shí)間：2014-10-08 18:35:13 閱讀次數(shù)：3319次
引言
C語(yǔ)言，C++語(yǔ)言等軟件編程語(yǔ)言吸引我們的一個(gè)很重要的原因是他們都能提供非常豐富的函數(shù)庫(kù)供我們使用，大大提高coding的效率。
但是像verilogHDL等HDL語(yǔ)言這方面做的比較弱，尤其是可綜合的語(yǔ)法，基本沒(méi)有通用的模塊庫(kù)供我們使用，所以編碼效率會(huì)比較低。如果我們把平時(shí)經(jīng)常使用的一些模塊積累起來(lái)，慢慢的標(biāo)準(zhǔn)化，這樣以后我們?cè)僭O(shè)計(jì)新的電路時(shí)，就會(huì)方便很多，今天就是開(kāi)始。
1，判斷兩個(gè)信號(hào)是否相等
function Fcompare;
input valid_a,valid_b;
input [31:0] a,b;
Fcompare = valid_a & valid_b & (({32{valid_a}} & a) == ({32{valid_b}} & b));
endfunction
2，對(duì)一個(gè)one-hot的值，得到是對(duì)應(yīng)bit的十進(jìn)制數(shù)
function [2:0] Fcode_8b;
input [7:0] one_hot;
Fcode_8b =( one_hot[0] ? 3'd0 :
one_hot[1] ? 3'd1 :
one_hot[2] ? 3'd2 :
one_hot[3] ? 3'd3 :
one_hot[4] ? 3'd4 :
one_hot[5] ? 3'd5 :
one_hot[6] ? 3'd6 :
one_hot[7] ? 3'd7 : 3'd0;
);
endfunction
3，上面函數(shù)的反向功能
function [7:0] Fdecode_8b;
input [2:0] value;
Fdecode_8b =( value==3'd7,value==3'd6,value==3'd5,value==3'd4,value==3'd3,value==3'd2,value==3'd1,value==3'd0 );
endfunction
4，clock gage
在實(shí)際的電路設(shè)計(jì)中，低功耗（low-power）是我們必須時(shí)刻都需要謹(jǐn)記在心的一條法則，這條法則的具體實(shí)現(xiàn)中最重要的就是clock gage了。
但是一般情況下DC會(huì)提供專(zhuān)門(mén)的gating cell，在做仿真時(shí)，我們還是需要一個(gè)簡(jiǎn)單的模型。
module clk_gate
(
input enable,
input clk,
output clk_o
);
reg not_gate;
always @(enable or clk)
if(~clk)
not_gate = enable;
assign clk_o = clk & not_gate;
endmodule
5，獲得信號(hào)的上升沿
module sig_posedge
(
input clk,
input signal,
output signal_posedge
);
reg tmp_r;
always @(posedge clk)
tmp_r <= signal;
assign signal_posedge = signal & ~tmp_r;
endmodule
6，獲得信號(hào)的下降沿
module sig_negedge
(
input clk,
input signal,
output signal_negedge
);
reg tmp_r;
always @(posedge clk)
tmp_r <= signal;
assign signal_negedge = ~signal & tmp_r;
endmodule
7，round-robin arbiter（2選1）
function [1:0] Fround_robin_2;
input [1:0] req,req_en,grant_en;
input priority_in;
reg rq_a,rq_b,grant_a,grant_b,prio_a,prio_b;
begin
{rq_a,rq_b} = req;
{prio_b,prio_a} = {priority_in==1'b1,priority_in==1'b0};
grant_a = ( prio_a & rq_a |
prio_b & rq_a & ~rq_b);
grant_b = ( prio_b & rq_b |
prio_a & rq_b & ~rq_a);
Fround_robin_2 = {grant_b,grant_a} & req_en & grant_en;
end
endfunction
8，round-robin arbiter（4選1）
function [3:0] Fround_robin_4;
input [3:0] req,req_en,grant_en;
input [1:0] priority_in;
reg rq_a,rq_b,rq_c,rq_d;
reg grant_a,grant_b,grant_c,grant_d;
reg prio_a,prio_b,prio_c,prio_d;
begin
{rq_d,rq_c,rq_b,rq_a} = req;
{prio_d,prio_c,prio_b,prio_a} = {priority_in==2'b11,priority_in==2'b10,priority_in==2'b01,priority_in==2'b00};
grant_a = ( prio_a & rq_a |
prio_b & rq_a & ~rq_b & ~rq_c & ~rq_d |
prio_c & rq_a & ~rq_c & ~rq_d |
prio_d & rq_a & ~rq_d);
grant_b = ( prio_b & rq_b |
prio_c & rq_b & ~rq_c & ~rq_d & ~rq_a |
prio_d & rq_b & ~rq_d & ~rq_a |
prio_a & rq_b & ~rq_a);
grant_c = ( prio_c & rq_c |
prio_d & rq_c & ~rq_d & ~rq_a & ~rq_b |
prio_a & rq_c & ~rq_a & ~rq_b |
prio_b & rq_c & ~rq_b);
grant_d = ( prio_d & rq_d |
prio_a & rq_d & ~rq_a & ~rq_b & ~rq_c |
prio_b & rq_d & ~rq_b & ~rq_c |
prio_c & rq_d & ~rq_c);
Fround_robin_4 = {grant_d,grant_c,grant_b,grant_a} & req_en & grant_en;
end
endfunction
9，round-robin arbiter（8選1）
function [7:0] Fround_robin_8;
input [7:0] req,req_en,grant_en;
input [2:0] priority_in;
reg rq_a,rq_b,rq_c,rq_d,rq_e,rq_f,rq_g,rq_h;
reg grant_a,grant_b,grant_c,grant_d,grant_e,grant_f,grant_g,grant_h;
reg prio_a,prio_b,prio_c,prio_d,prio_e,prio_f,prio_g,prio_h;
begin
{rq_h,rq_g,rq_f,rq_e,rq_d,rq_c,rq_b,rq_a} = req;
{prio_h,prio_g,prio_f,prio_e,prio_d,prio_c,prio_b,prio_a} = {priority_in==3'b111,priority_in==3'b110,priority_in==3'b101,priority_in==3'b100,priority_in==3'b011,priority_in==3'b010,priority_in==3'b001,priority_in==3'b000};
grant_a = ( rq_a &
(prio_a
|prio_b & ~rq_b & ~rq_c & ~rq_d & ~rq_e & ~rq_f & ~rq_g & ~rq_h
|prio_c & ~rq_c & ~rq_d & ~rq_e & ~rq_f & ~rq_g & ~rq_h
|prio_d & ~rq_d & ~rq_e & ~rq_f & ~rq_g & ~rq_h
|prio_e & ~rq_e & ~rq_f & ~rq_g & ~rq_h
|prio_f & ~rq_f & ~rq_g & ~rq_h
|prio_g & ~rq_g & ~rq_h
|prio_h & ~rq_h);
grant_b = ( rq_b &
(prio_b
|prio_c & ~rq_c & ~rq_d & ~rq_e & ~rq_f & ~rq_g & ~rq_h & ~rq_a
|prio_d & ~rq_d & ~rq_e & ~rq_f & ~rq_g & ~rq_h & ~rq_a
|prio_e & ~rq_e & ~rq_f & ~rq_g & ~rq_h & ~rq_a
|prio_f & ~rq_f & ~rq_g & ~rq_h & ~rq_a
|prio_g & ~rq_g & ~rq_h & ~rq_a
|prio_h & ~rq_h & ~rq_a
|prio_a & ~rq_a);
grant_c = ( rq_c &
(prio_c
|prio_d & ~rq_d & ~rq_e & ~rq_f & ~rq_g & ~rq_h & ~rq_a & ~rq_b
|prio_e & ~rq_e & ~rq_f & ~rq_g & ~rq_h & ~rq_a & ~rq_b
|prio_f & ~rq_f & ~rq_g & ~rq_h & ~rq_a & ~rq_b
|prio_g & ~rq_g & ~rq_h & ~rq_a & ~rq_b
|prio_h & ~rq_h & ~rq_a & ~rq_b
|prio_a & ~rq_a & ~rq_b
|prio_b & ~rq_b);
grant_d = ( rq_d &
(prio_d
|prio_e & ~rq_e & ~rq_f & ~rq_g & ~rq_h & ~rq_a & ~rq_b & ~rq_c
|prio_f & ~rq_f & ~rq_g & ~rq_h & ~rq_a & ~rq_b & ~rq_c
|prio_g & ~rq_g & ~rq_h & ~rq_a & ~rq_b & ~rq_c
|prio_h & ~rq_h & ~rq_a & ~rq_b & ~rq_c
|prio_a & ~rq_a & ~rq_b & ~rq_c
|prio_b & ~rq_b & ~rq_c
|prio_c & ~rq_c);
grant_e = ( rq_e &
(prio_e
|prio_f & ~rq_f & ~rq_g & ~rq_h & ~rq_a & ~rq_b & ~rq_c & ~rq_d
|prio_g & ~rq_g & ~rq_h & ~rq_a & ~rq_b & ~rq_c & ~rq_d
|prio_h & ~rq_h & ~rq_a & ~rq_b & ~rq_c & ~rq_d
|prio_a & ~rq_a & ~rq_b & ~rq_c & ~rq_d
|prio_b & ~rq_b & ~rq_c & ~rq_d
|prio_c & ~rq_c & ~rq_d
|prio_d & ~rq_d);
grant_f = ( rq_f &
(prio_f
|prio_g & ~rq_g & ~rq_h & ~rq_a & ~rq_b & ~rq_c & ~rq_d & ~rq_e
|prio_h & ~rq_h & ~rq_a & ~rq_b & ~rq_c & ~rq_d & ~rq_e
|prio_a & ~rq_a & ~rq_b & ~rq_c & ~rq_d & ~rq_e
|prio_b & ~rq_b & ~rq_c & ~rq_d & ~rq_e
|prio_c & ~rq_c & ~rq_d & ~rq_e
|prio_d & ~rq_d & ~rq_e
|prio_e & ~rq_e);
grant_g = ( rq_g &
(prio_g
|prio_h & ~rq_h & ~rq_a & ~rq_b & ~rq_c & ~rq_d & ~rq_e & ~rq_f
|prio_a & ~rq_a & ~rq_b & ~rq_c & ~rq_d & ~rq_e & ~rq_f
|prio_b & ~rq_b & ~rq_c & ~rq_d & ~rq_e & ~rq_f
|prio_c & ~rq_c & ~rq_d & ~rq_e & ~rq_f
|prio_d & ~rq_d & ~rq_e & ~rq_f
|prio_e & ~rq_e & ~rq_f
|prio_f & ~rq_f);
grant_h = ( rq_h &
(prio_h
|prio_a & ~rq_a & ~rq_b & ~rq_c & ~rq_d & ~rq_e & ~rq_f & ~rq_g
|prio_b & ~rq_b & ~rq_c & ~rq_d & ~rq_e & ~rq_f & ~rq_g
|prio_c & ~rq_c & ~rq_d & ~rq_e & ~rq_f & ~rq_g
|prio_d & ~rq_d & ~rq_e & ~rq_f & ~rq_g
|prio_e & ~rq_e & ~rq_f & ~rq_g
|prio_f & ~rq_f & ~rq_g
|prio_g & ~rq_g);
Fround_robin_8 = {grant_h,grant_g,grant_f,grant_e,grant_d,grant_c,grant_b,grant_a} & req_en & grant_en;
end
endfunction
10，簡(jiǎn)易同步fifo
module simple_syn_fifo
#(
parameter WIDTH = 32,
parameter DEPTH = 4,
parameter PTR_WIDTH = 2
)
(
input clk,
input rst_n,
input ren,
input wen,
input [WIDTH-1:0] din,
output full,
output empty,
output valid,
output [WIDTH-1:0] dout
);
reg [WIDTH-1:0] mem_r[0:DEPTH-1];
reg [PTR_WIDTH-1:0] rptr_r;
reg [PTR_WIDTH-1:0] wptr_r;
reg [PTR_WIDTH:0] flag_r;
always @(posedge clk)
if(wen)
mem_r[wptr_r] <= din;
always @(posedge clk)
if(~rst_n)
wptr_r <= (PTR_WIDTH-1)'d0;
else if(wen)
wptr_r <= wptr_r + 1'b1;
always @(posedge clk)
if(~rst_n)
rptr_r <= (PTR_WIDTH-1)'d0;
else if(wen)
rptr_r <= rptr_r + 1'b1;
always @(posedge clk)
if(~rst_n)
flag_r <= PTR_WIDTH'd0;
else if(wen & ~ren)
flag_r <= flag_r + 1'b1;
else if(~wen & ren)
flag_r <= flag_r - 1'b1;
assign dout = mem_r[rptr_r];
assign full = (flag_r >= DEPTH);
assign empty = (flag_r == PTR_WIDTH'd0);
assign valid = ren;
endmodule
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